VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and ...
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VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
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Add this copy of VLSI Fault Modeling and Testing Techniques to cart. $89.52, new condition, Sold by Ingram Customer Returns Center rated 5.0 out of 5 stars, ships from NV, USA, published 1993 by Ablex Publishing Corporation.
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Add this copy of VLSI Fault Modeling and Testing Techniques to cart. $97.94, new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 1993 by Praeger.
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New. Sewn binding. Cloth over boards. With dust jacket. 208 p. Contains: Unspecified. VLSI Design Automation Series. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
Add this copy of VLSI Fault Modeling and Testing Techniques to cart. $97.94, like new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 1993 by Praeger.
Choose your shipping method in Checkout. Costs may vary based on destination.
Seller's Description:
Fine. Sewn binding. Cloth over boards. With dust jacket. 208 p. Contains: Unspecified. VLSI Design Automation Series. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
